Mobileye EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars.

Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges

We’re looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.

What will your job look like:

• Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
• Writing design constraints (SDC) for FC/IP/Block levels for all modes.
• Involved in chip architecture definition for functional & DFT domains.
• Working in close collaboration with the front-end & architecture team.
• Working with engineers to identify and overcome roadblocks and obstacles.
• Defining AC timing from spec to implementation.
• Supporting complex clock structures.
  
  

All you need is:

• BSc/MSc in Electrical Engineering/Computer Science.
• STA Expert (Prime-Time/Signoff).
• 8 years of experience in VLSI backend (RTL2GDS).
• 5 years of experience in full chip STA on complex SoCs.
• Expert knowledge in timing closure & signoff methodologies.
• Experience with DFT architecture, Async timing concepts & verification.
• Experience in technically leading complex backend activities, preferably of complete SoC's.
• Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs).
  
  

Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!