Are you an experienced VLSI physical design engineer with proven managerial capabilities and highly passionate about developing cutting edge technology? Then you belong with us!

Here at Ceva, we are developing state-of-the-art DSP, AI processors and HW accelerator ASIC projects in AI, Vision, Wireless, and Base-stations areas.

We are seeking a highly skilled and motivated VLSI Backend Team Leader to join and lead our dynamic team.

As part of this position, you will lead a team of experienced engineers working on parallel projects, and play a crucial role in the design and implementation of complex designs, flow development, and the latest technology node bring-up and integration.

The Backend team leader will be required to do 50% hands on work and 50% managerial work.

Requirements:

• B.Sc. / M.Sc. in Electrical Engineering from a leading institute
• At least 10 years of experience as a VLSI Backend Engineer
• In-depth knowledge of Synthesis, P&R, and STA flows
• Hands-on experience of full RTL to GDS-II flow for complex designs
• Experience in development in advanced nodes (7nm and below)
• Experience in scripting using TCL and Python.

Advantage:

• Previous managerial experience – not a must.
• Top-level integration experience for multi-partition SOC.
• In-depth knowledge of RTL (Verilog/System Verilog)

Personality:

• Self-motivated and self-directed, proactive
• Ability to achieve results in a fast-moving, agile flow, and dynamic environment, both locally and across the organization
• Ability to troubleshoot and analyze complex problems
• Excellent communication skills, both verbally and in writing

Team player